clock-to-output delay

См. также в других словарях:

• Clock distribution network — In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. The clock distribution network (or clock tree, when this network forms a tree) distributes the clock signal(s) from… …   Wikipedia

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• Phase-locked loop — PLL redirects here. For other uses, see PLL (disambiguation). A phase locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. It is an electronic… …   Wikipedia